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`timescale 1ns / 1ps

//***********************************Entity Declaration*******************************
module ETH10G_PCS_GT_USRCLK_SOURCE
(
    input  wire  Q1_CLK0_GTREFCLK_PAD_N_IN,
    input  wire  Q1_CLK0_GTREFCLK_PAD_P_IN,
    output wire  Q1_CLK0_GTREFCLK_OUT,
 
    output          GT0_TXUSRCLK_OUT,
    output          GT0_TXUSRCLK2_OUT,
    input           GT0_TXOUTCLK_IN,
    output          GT0_RXUSRCLK_OUT,
    output          GT0_RXUSRCLK2_OUT,
    input           GT0_RXOUTCLK_IN,
    input	          DRPCLK_IN,
    output          DRPCLK_OUT

);


`define DLY #1

//*********************************Wire Declarations**********************************

    wire            tied_to_ground_i;
    wire            tied_to_vcc_i;
 
    wire            gt0_txoutclk_i; 
    wire            gt0_rxoutclk_i;
    
    wire            q1_clk0_gtrefclk;

    wire            gt0_txusrclk_i;
    wire            gt0_rxusrclk_i;

//*********************************** Beginning of Code *******************************

    //  Static signal Assigments    
    assign tied_to_ground_i             = 1'b0;
    assign tied_to_vcc_i                = 1'b1;
    assign gt0_txoutclk_i = GT0_TXOUTCLK_IN;
    assign gt0_rxoutclk_i = GT0_RXOUTCLK_IN;
     
    assign Q1_CLK0_GTREFCLK_OUT = q1_clk0_gtrefclk;

    //IBUFDS_GTE2
    IBUFDS_GTE2 ibufds_instQ1_CLK0  
    (
        .O               (q1_clk0_gtrefclk),
        .ODIV2           (),
        .CEB             (tied_to_ground_i),
        .I               (Q1_CLK0_GTREFCLK_PAD_P_IN),
        .IB              (Q1_CLK0_GTREFCLK_PAD_N_IN)
    );

    BUFG txoutclk_bufg0_i
    (
        .I                              (gt0_txoutclk_i),
        .O                              (gt0_txusrclk_i)
    );


    BUFG rxoutclk_bufg1_i
    (
        .I                              (gt0_rxoutclk_i),
        .O                              (gt0_rxusrclk_i)
    );




 
    assign GT0_TXUSRCLK_OUT = gt0_txusrclk_i;
    assign GT0_TXUSRCLK2_OUT = gt0_txusrclk_i;
    assign GT0_RXUSRCLK_OUT = gt0_rxusrclk_i;
    assign GT0_RXUSRCLK2_OUT = gt0_rxusrclk_i;

endmodule

